History of Apple Computer Models&nbsp;&nbsp;

Mac Mini (Sep 2006)

CPU: Core Duo "Yonah" T2300 (1.66 GHz) or T2400 (1.83 GHz)

L2-Cache: 2M

Bus: 667 MHz

Memory: 667 MHz PC2-5300 DDR2 SDRAM

Mac Mini (Aug 2007)

CPU: Core Duo "Yonah" T5600 (1.83 GHz) or T7200 (2.0 GHz)

L2-Cache: 2M

Bus: 667 MHz

Memory: 667 MHz PC2-5300 DDR2 SDRAM

Mac Mini (nVidia graphics)

CPU: Core 2 Duo "Penryn" P7350 (2.0 GHz) or P8400 (2.26 GHz)

L2-Cache: 3M

Bus: 1.066 GT/sec

Memory: 1.066 GHz PC3-8500 DDR3 SDRAM

Mac Mini (Oct 2009)

CPU: Core 2 Duo "Penryn" P7550 (2.26 GHz), P8700 (2.53 GHz), or P8800 (2.66 GHz)

L2-Cache: 3M

Bus: 1.066 GT/sec

Memory: 1.066 GHz PC3-8500 DDR3 SDRAM

Mac Mini ("Unibody", June 2010)

CPU: Core 2 Duo "Penryn" P8600 (2.4 GHz) or P8800 (2.66 GHz)

L2-Cache: 3M

Bus: 1.066 GT/sec

Memory: 1.066 GHz PC3-8500 DDR3 SDRAM

iMac G4 (original with 15" screen), 2002 Jan 7

Details for iMac

CPU: PowerPC "G4" 7441 at 700 MHz or 7445 at 800 MHz

L2-Cache: 256K

Bus: 100 MT/sec

Memory: PC133 SDRAM (133 MT/sec)

EveryMac profiles: 700 MHz, 800 MHz

Several iMac systems to be added here

iMac (17" and 20" core 2), 2006 Jan 10

CPU: Core Duo "Yonah" T2400 (1.83 GHz) or T2500 (2.0 GHz) (2006 Jan 5: $294 or $423)

L2-Cache: 2M (shared by both cores)

Bus: 667 MT/sec

Memory: 667 MHz PC2-5300 DDR2 SDRAM

EveryMac profiles: 17-inch, 20-inch

iMac (17", 20" and 24" core 2), 2006 Sep 6

CPU: Core 2 Duo "Merom" T7200 (2.0 GHz) or T7400 (2.16 GHz) (2006 Aug 28: $294 or $423)

L2-Cache: 4M (shared by both cores)

Bus: 667 MT/sec

Memory: 667 MHz PC2-5300 DDR2 SDRAM

EveryMac profiles: 17-inch, 20-inch, 24-inch

There was also a model for education customers only, with a 1.83-GHz processor. It was $899, but only for purchase by institutions (not even students or faculty). A profile is here.

iMac (aluminum), 2007 Aug 7

CPU: Core 2 Duo "Merom" T7300 (2.0 GHz), T7700 (2.4 GHz) (2007 May 9: $241 or $530) or "Merom XE" X7900 (2.8 GHz) (2007 Aug 22: $851)

L2-Cache: 4M (2.0 and 2.4 GHz models) or 6M (2.8 GHz model) (shared by both cores)

Bus: 800 MT/sec (2.0 and 2.4 GHz) or 1066 MT/sec (2.8 GHz model)

Memory: 667 MHz PC2-5300 DDR2 SDRAM

EveryMac profiles: 20-inch 2.0 GHz, 24-inch 2.8 GHz

iMac (aluminum), 2008 Apr 28

CPU: Core 2 Duo "Penryn" E8135 (2.4 GHz), E8335 (2.66 GHz), E8235 (2.8 GHz) or "Penryn XE" E8435 (3.06 GHz) (prices unknown)

L2-Cache: 6M (shared by both cores)

Bus: 1066 MT/sec (2.8 GHz model)

Memory: 800 MHz PC2-6400 DDR2 SDRAM

EveryMac profiles: 20-inch 2.4 GHz, 24-inch 3.06 GHz

iMac (aluminum), 2009 March 3

CPU: Core 2 Duo "Penryn" E8135 (2.66 GHz), E8335 (2.93 GHz) or "Penryn XE" E8435 (3.06 GHz) (E8435 released 2008 Aug 10 at $266)

Cores/Threads: All models have 2 cores and 2 threads.

L2-Cache: 6M (shared by both cores)

Bus: 1066 MT/sec

Memory: 1.066 GHz PC3-8500 DDR3 SDRAM

EveryMac profiles: 20-inch 2.66 GHz, 24-inch 2.66 GHz, 24-inch 2.93 GHz, 24-inch 3.06 GHz

On April 7 Apple added a 20-inch, 2.0-GHz model for education customers only. A profile courtesy of EveryMac can be found here. Its price was $899, but individuals could not buy it, even if they were students or faculty — it could only be bought by institutions.

iMac (21.5 / 27), 2009 Oct 20

CPU: Core 2 Duo "Penryn XE" E8435 (3.06 GHz) or E8600 (3.33 GHz) or Core i5 750 (2.66 GHz) or Core i7 860 (2.8 GHz) (i5 and i7 both released 2009 Sep 8 at $196 and $284)

Cores/Threads: All models have 2 cores; "Core 2 Duo" models have 2 threads; "Core i5" and "Core i7" models have 4 threads.

L2-Cache: 3M (on E8435), 6M (on Exxxx) or 8M (on Core i5 and i7) (shared by all cores)

Bus: 1066 MT/sec (2.8 GHz model)

Memory: 1.066 GHz PC3-8500 DDR3 SDRAM

iMac (ATI graphics), 2010 Jul 27

EveryMac profiles: 21.5-inch 3.06 GHz, 27-inch 3.06 GHz, 27-inch Core i5

CPU: Core i3 "Clarkdale" 540 (3.06 GHz dual-core) or 550 (3.2 GHz dual-core) or Core i5 "Lynnfield" 760 (2.8 GHz quad-core) or 680 (3.6 GHz dual-core) or Core i7 875K (2.93 GHz quad-core)

Cores/Threads: all "dual-core" models have 2 cores and 4 threads; "Core i5 quad-core" model has 4 cores and 4 threads; "Core i7" model has 4 cores and 8 threads.

L2-Cache: 2M per core (i.e. 4M or 8M total)

Bus: 1333 MT/sec

Memory: 1.333 GHz PC3-10600 DDR3 SDRAM

EveryMac profiles: 21.5-inch 3.06 GHz Core i3 21.5-inch 3.2 GHz Core i3 27-inch 3.2 GHz Core i3 27-inch 2.8 GHz Core i5

Details for iBook and MacBook

This was a new line created in 1999 as a consumer-oriented portable. It initially had a substantially different look and feel from the PowerBooks, but has gradually converged over the following 10 years.

iBook G4 (12" and 14")

CPU: PowerPC "G4" 7457 at 800 MHz (12" model) or 933 MHz (14" model)

L2-Cache: 256K

Bus: 133 MT/sec

Memory: PC2100 DDR SDRAM (267 MT/sec)

Details for Powerbook and MacBook Pro

The never-shipped 1.67 GHz MacBook Pro 15"

CPU: Core Duo "Yonah" L2400 (1.67 GHz) (2006 Jan 5: $316)

L2-Cache: 2M (shared by both cores)

Bus: 667 MT/sec

Memory: 667 MHz PC2-5300 DDR2 SO-DIMM

MacBook Pro, 2006 Feb 14 and 2006 Apr 24

This system never shipped. On 2006 Feb 14, Apple announced that the MacBook Pro line (which had not yet shipped) would feature 1.83, 2.0 and 2.16 GHz processors, thus eliminating the 1.67 GHz version.

CPU: Core Duo "Yonah" T2400 (1.83 GHz), T2500 (2.0 GHz) or T2600 (2.16 GHz) (2006 Jan 5: $294 - $637)

L2-Cache: 2M (shared by both cores)

Bus: 667 MT/sec

Memory: 667 MHz PC2-5300 DDR2 SO-DIMM

AppleMatters profile

lowendmac profiles: 15-inch, 17-inch

MacBook Pro, 2006 Oct 24

CPU: Core 2 Duo "Merom" T7400 (2.16 GHz) or T7600 (2.33 GHz) (2006 Aug 28: $423, $637)

L2-Cache: 4M (shared by both cores)

Bus: 667 MT/sec

Memory: 667 MHz PC2-5300 DDR2 SDRAM

EveryMac's profiles: 2.16 15", 2.33 17"

lowendmac profiles: 15-inch, 17-inch

MacBook Pro (Santa Rosa), 2007 Jun 5

CPU: Core 2 Duo "Merom" T7500 (2.2 GHz) or T7700 (2.4 GHz) (2007 May 9: $316, $530)

L2-Cache: 4M (shared by both cores)

Bus: 800 MT/sec

Memory: 667 MHz PC2-5300 DDR2 SDRAM

lowendmac profiles: 15-inch 17-inch

EveryMac's profiles: 2.2 15'', 2.4 17''

MacBook Pro (17'' 2.6 GHz option), 2007 Nov 1

CPU: Core 2 Duo "Merom" T7800 (2.6 GHz) (2007 Sep 2: $530)

L2-Cache: 4M (shared by both cores)

Bus: 800 MT/sec

Memory: 667 MHz PC2-5300 DDR2 SDRAM

EveryMac's profile (which only makes brief mention of the 2.6 GHz version)

MacBook Pro (Penryn), 2008 Feb 26 (2.5 and 2.6 GHz versions)

CPU: Core 2 Duo "Penryn" T8300 (2.4 GHz) or T9300 (2.5 GHz) or T9500 (2.6 GHz) (2008 Jan 6: $241, $316, $530)

L2-Cache: 3M (2.4 GHz models) or 6M (faster models) (shared by both cores)

Bus: 800 MT/sec

Memory: 667 MHz PC2-5300 DDR2 SDRAM

lowendmac profiles: 15-inch 17-inch

EveryMac's profiles: 2.4 15'' 2.5 15'', 2.6 17'' (which mentions the 2.6 GHz option)

MacBook Pro 15'' (Unibody), 2008 Oct 14

CPU: Core 2 Duo "Penryn" P8600 (2.4 GHz) (2008 Jun 13: $241), T9400 (2.533 GHz) or T9600 (2.8 GHz) (both 2008 Jul 14: $316, $530)

L2-Cache: 3M (2.4 model) or 6M (higher models) (cache is shared by both cores)

Bus: 1.066 GT/sec

Memory: 1.066 GHz PC2-8500 DDR2 SDRAM

lowendmac profiles: 15-inch

NOTE: In 2008 Oct, the 17-inch MacBook Pro still had the same CPU, bus and memory specs as the 2008 Feb 26 version, but its screen and hard drive were changed in conjunction with the all-new "unibody" 15'' model.

MacBook Pro (17-inch Unibody, January 2009)

CPU: Core 2 Duo "Penryn" T9550 (2.66 GHz) or T9800 (2.93 GHz) ()

L2-Cache: 6M

Bus: 1.066 GT/sec

Memory: 1.066 GHz PC2-8500 DDR2 SDRAM

lowendmac profiles: 17-inch

EveryMac's profile: 2.66 17''

MacBook Pro (15-inch Unibody, March 2009)

CPU: Core 2 Duo "Penryn" T9550 (2.66 GHz) ()

L2-Cache: 6M

Bus: 1.066 GT/sec

Memory: 1.066 GHz PC2-8500 DDR2 SDRAM

EveryMac's profile: 2.66 15''

MacBook Pro (SD card slot, June 2009)

CPU: Core 2 Duo "Penryn" P8400 (2.26 GHz), P8700 (2.53 GHz), P8800 (2.66 GHz), T9600 (2.8 GHz), or T9900 (3.06 GHz) (20080714: $209 - $530)

Cores/Threads: All models have 2 cores and 2 threads.

L2-Cache: 3M (2.26, 2.53 and 2.66 GHz models) or 6M (2.8 and 3.06 GHz models)

Bus: 1.066 GT/sec

Memory: 1.066 GHz PC2-8500 DDR2 SDRAM

lowendmac profiles: 13-inch 15-inch 17-inch

EveryMac's profiles: 2.26 13'' 2.53 13'' 2.53 15'' 2.66 15'' 2.8 15'' 2.8 and 3.06 17''

MacBook Pro (April 2010)

CPU: Core 2 Duo "Penryn" P8600 (2.4 GHz) or P8800 (2.66 GHz) (20080613: $241)

or Core i5 "Arrandale" 520M (2.4-2.93 GHz) or 540M (2.53-3.06 GHz) (20100107: $225, $257)

or Core i7 620M (2.66-3.33 GHz) (20100107: $332)

Cores/Threads: All models have 2 cores; "Core 2 Duo" models have 2 threads; "Core i5" and "Core i7" models have 4 threads.

L2-Cache: 3M (Core 2 Duo and Core i5 models) or 4M (2.66 Core i7 model)

Bus: 1.066 GT/sec

Memory: 1.066 GHz PC3-8500 DDR3 SDRAM

EveryMac's profiles: 2.4 13'' 2.66 13'' 2.4 15'' 2.53 15'' 2.66 15'' 2.53 and 2.66 17''

MacBook Pro (2.8 GHz option), Oct 2010

CPU: Core i7 640M (2.8-3.46 GHz) (20100926: $346)

Cores/Threads: 2 cores/4 threads.

L2-Cache: 4M

Bus: 1.066 GT/sec

Memory: 1.066 GHz PC3-8500 DDR3 SDRAM

MacBook Pro (Feb 2011)

CPU: 13'' models have Core i5 "Sandy Bridge" 2410M (2.3-2.9 GHz), or Core i7 2620M (2.7-3.4 GHz) (20110221: $xxx, $346)

15'' and 17'' models have Core i7 "Sandy Bridge" 2630QM (2.0-2.9 GHz), 2720QM (2.2-3.3 GHz) or 2820QM (2.3-3.4 GHz) (20110221: $XXX, $378, $568)

Cores/Threads: 13'' models have 2 cores and 4 threads; 15'' and 17'' models have 4 cores and 8 threads

L3-Cache: 3MB (13'' with Core i5), 4MB (13'' with Core i7), 6MB (2.0 GHz and 2.2 GHz quad-core), or 8MB (2.3 GHz quad-core)

Bus: 1.333 GT/sec

Memory: 1.333 GHz DDR3 SDRAM

lowendmac profiles: 13-inch 15-inch 17-inch

Idle Speculations on MacBook Pro

(none at present)

Details for PowerMac and Mac Pro

Power Mac G3 (Blue and White), 1999 Jan 5

CPU: IBM PowerPC 750 (300, 350 or 400 MHz)

L2-Cache: 512K (300 MHz model) or 1M (faster models)

Bus: 100 MHz

Memory: PC100 SDRAM

Power Mac G4 450, 1999 Aug 31

CPU: IBM PowerPC 750 (450 MHz)

L2-Cache: 1M

Bus: 100 MHz

Memory: PC100 SDRAM

Power Mac G4 "Gigabit Ethernet", 2000 Feb 16

CPU: 2x IBM PowerPC 750 (450 or 500 MHz)

L2-Cache: 2M (1M per processor)

Bus: 100 MHz

Memory: PC100 SDRAM

Power Mac G4 "Digital Audio", 2001 Jan 9

CPU: Motorola 7410 "Nitro" (single 466 MHz or dual 533 MHz)

L2-Cache: 1M (or 2M for dual 533 model)

Bus: 133 MHz

Memory: PC133 SDRAM

Power Mac G4 "Digital Audio", 2001 Feb

EveryMac profiles: 466, 533

CPU: Motorola 7450 "V'ger" (667 or 733 MHz)

L2-Cache: 1M

Bus: 133 MHz

Memory: PC133 SDRAM

Power Mac G4 "Quicksilver", 2001 Jul 18

EveryMac profiles: 667, 733

CPU: Motorola 7450 "V'ger" (733 or 867 MHz)

CPU: 2x Motorola 7450 "V'ger" (800 MHz)

L2-Cache: 1M (2M for dual 800 model)

Bus: 133 MHz

Memory: PC133 SDRAM

Power Mac G4 "Quicksilver", 2002 Jan 28

EveryMac profiles: 733, 867, dual 800

CPU: Motorola 7455 "Apollo 6" (800 or 933 MHz)

CPU: 2x Motorola 7455 "Apollo 6" (1.0 GHz)

L2-Cache: none on 800 MHz model; 2M on 933 MHz model; 4M (2M per processor) on 1.0 GHz model

Bus: 133 MHz

Memory: PC133 SDRAM

Power Mac G4 (Mirror Drive Doors), 2002 Aug 13

EveryMac profiles: 800, 933, dual 1.0

CPU: 2x Motorola 7455 "Apollo 6" (867 MHz, 1.0 GHz or 1.25 GHz)

L2-Cache: 1M (867 and 1.0 GHz models) or 2M (1.25 GHz model)

Bus: 133 MHz (867 model), 167 MHz (faster models)

Memory: 266 MHz PC2100 DDR SDRAM (867 model) or 333 MHz PC2700 DDR SDRAM (faster models)

Power Mac G4 (Firewire 800), 2003 Jan 28

EveryMac profiles: 867, 1.0, 1.25

CPU: Motorola 7455 "Apollo 6" (single 1.0 GHz, dual 1.25 or dual 1.42 GHz)

L2-Cache: 1M (1.0 GHz model), 2M (dual 1.25 GHz model), or 4M (dual 1.42 GHz model)

Bus: 133 MHz (1.0 GHz model), 167 MHz (faster models)

Memory: 266 MHz PC2100 DDR SDRAM (1.0 GHz model) or 333 MHz PC2700 DDR SDRAM (faster models)

EveryMac profiles: 1.0, 1.25, 1.42

PowerMac G5, 2003 Jun 23

CPU: IBM PowerPC 970 (single 1.6, single 1.8, or dual 2.0 GHz)

L2-Cache: 512K

Bus: 800 MHz, 900 Mhz or 1.0 GHz

Memory: 333 MHz PC2700 DDR RAM (1.6 GHz model) or 400 MHz PC3200 DDR RAM (faster models)

PowerMac G5 (PCI-X 2), 2004 Jun 9

EveryMac profiles: 1.6, 1.8, 2.0

CPU: 2x IBM PowerPC 970fx (1.8, 2.0 or 2.5 GHz)

L2-Cache: 1M (512K per CPU)

Bus: 900 Mhz, 1.0 GHz or 1.25 GHz

Memory: 400 MHz PC3200 DDR RAM

PowerMac G5 Single, 2004 Oct 19

EveryMac profiles: 1.8, 2.0, 2.5

CPU: IBM PowerPC 970fx (1.8 GHz)

L2-Cache: 512K

Bus: 600 Mhz

Memory: 400 MHz PC3200 RAM

PowerMac G5, 2005 Apr 27

CPU: 2x IBM PowerPC 970fx (2.0, 2.3 or 2.7 GHz)

L2-Cache: 1M (512K per CPU)

Bus: 1.0, 1.15 or 1.35 GHz

Memory: 400 MHz PC3200 DDR RAM

PowerMac G5 Dual, 2005 Oct 19

EveryMac profiles: 2.0, 2.3, 2.7

CPU: IBM PowerPC 970MP "Antares" (2.0 or 2.3 GHz)

L2-Cache: 2M (1M per core)

Bus: 1.0 or 1.15 GHz

Memory: 533 MHz PC2-4200 DDR2

PowerMac G5 Quad, 2005 Oct 19

EveryMac profiles: 2.0, 2.3

CPU: 2x IBM PowerPC 970MP "Antares" (2.5 GHz)

L2-Cache: 4M (1M per core)

Bus: 1.25 GHz

Memory: 533 MHz PC2-4200 DDR2

Mac Pro (Quad), 2006 Aug 7

CPU: 2x Intel Core 2 Duo "Woodcrest" 5130 (2.0 GHz), 5150 (2.66 GHz) or 5160 (3.0 GHz) (all 2006 Jun 26: $316 - $851)

L2-Cache: 8M (4M for each pair of cores)

Bus: 1.33 GT/sec

Memory: 667 MHz PC2-5300 DDR2 fully buffered (FB-DIMM) ECC RAM, dual channel (10.7 GB/s bandwidth)

Mac Pro 8-core, 2007 Apr 4

EveryMac's profile

CPU: 2x Intel Core 2 Quad "Clovertown" X5365 (3.0 GHz) (2007 April 4: $1350)

L2-Cache: 16M (each pair of cores shares 4M)

Bus: 1.33 GT/sec

Memory: 667 MHz PC2-5300 DDR2 fully buffered (FB-DIMM) ECC RAM, dual channel (10.7 GB/s bandwidth)

Mac Pro 8-core, 2008 Jan 8

CPU: 2x Intel Core 2 Quad "Harpertown" E5462 (2.8 GHz), E5472 (3.0 GHz) or X5482 (3.2 GHz) (all 2007 Nov 11: $797 or 851, $958, $1279)

Cores/Threads: All models have 8 cores and 8 threads.

L2-Cache: 24M (each pair of cores shares 6M)

Bus: 1.6 GT/sec

Memory: 800MHz DDR2 ECC fully buffered DIMM (FB-DIMM) RAM, dual channel (12.8 GB/s bandwidth)

Mac Pro "Gainestown Nehalem", 2009 Mar 3

CPU: 1x Xeon W3520 (2.66 GHz) or W3540 (2.93 GHz) ($284, $562)

or 2x Xeon E5520 (2.26 GHz), X5550 (2.66 GHz) or X5570 (2.93 GHz) ($373 - $1386)

Cores/Threads: Each Xeon CPU has 4 cores and 8 threads; thus the dual-CPU machines have 8 cores and 16 threads.

Cache: 256K L2 and 2M L3 per core (1 processor = 4 cores, i.e. either 9M or 18M total cache)

Bus: Controls memory directly; uses QuickPath Interconnect at 5.86 GT/sec (2.26 GHz 8-core model) or 6.4 GT/sec (all other models) for data transfer between one processor and the other, and between processor(s) and the video, hard drives and rest of the system.

Memory: 1066 MHz DDR3 ECC SDRAM, triple channel (25.6 GB/s bandwidth per CPU socket)

Mac Pro (late 2009 3.33 GHz), 2009 Dec 4

EveryMac profiles: Quad 2.66, Octo-core 2.26.

CPU: 1x Xeon X5590 (3.33 GHz) ($1600)

Cores/Threads: 4 physical cores, 8 threads.

Cache: 256K L2 and 2M L3 per core (1 processor = 4 cores, i.e. 9M total cache)

Bus: Controls memory directly; uses QuickPath Interconnect at 6.4 GT/sec for data transfer between one processor and the other, and between processor(s) and the video, hard drives and rest of the system.

Memory: 1066 MHz DDR3 ECC SDRAM, triple channel (25.6 GB/s bandwidth)

Mac Pro "Westmere", 2010 August

CPU: 1x Xeon W3530 (2.8 GHz 4-core), W3565 (3.2 GHz 4-core) or W3680 (3.33 GHz 6-core) ($unknown, $562, $999)

or 2x Xeon E5620 (2.4 GHz 4-core), X5650 (2.66 GHz 6-core) or X5670 (2.93 GHz 6-core) ($387, $996, $1440)

Cores/Threads: From 4 to 12 cores, with 2 threads per core.

Cache: most models have 256K L2 and 2M L3 per core (i.e. from 9M to 27M total cache); the 8-core (2x Xeon E5620) model has 256K L2 and 3M L3 cache per core (26M total cache).

Bus: Controls memory directly; uses QuickPath Interconnect at 4.8 GT/sec (2.8 GHz 4-core model), 5.86 GT/sec (2x 2.4 GHz 4-core) or 6.4 GT/sec (6-core and 12-core models) for data transfer between one processor and the other, and between processor(s) and the video, hard drives and rest of the system.

Memory: 1066 MHz DDR3 ECC SDRAM (4-core and 6-core systems)

or 1333 MHz DDR3 ECC SDRAM (8-core and 12-core systems)

triple channel (25.6 GB/s or 32 GB/s bandwidth per CPU socket)

Idle Speculations for Mac Pro

Late 2011 (speculation)

(updated in 2010 November)

Intel is expected to offer processors based on the Sandy Bridge microarchitecture to follow all of the current 32nm Nehalem processors. These will continue to use the 32-nm process but will add improvements to the core, notably a 256-bit vector capability to perform twice as many floating-point operations per clock cycle, and a high-speed inter-core ring bus design inherited from Beckton (Xeon 75xx series, see [76]). Both will aid tightly-coupled CPU-bound multicore workloads. However, this and other core changes will place higher demands on the cache and memory system, so it is unlikely the number of cores will change because the transistors and power are needed for cache and memory interface (however, the Inquirer predicts 8 cores and 20M of L3 cache, up from the present 4 or 6 cores and 8M or 12M, see [72]). On some Sandy Bridge products this transistor budget will include integrated GPU functions [67], discussed further in my MacBook Pro speculation, but Mac Pro is likely to continue shipping with a graphics card, and will probably have Xeon Sandy Bridge GPUs that either have no GPU at all, a disabled GPU, or perhaps the smaller GPU capability of the desktop-targetted Sandy Bridge products.

As of September 2010, the only specific Sandy Bridge designs that have been shown are mobile and desktop replacements; the best of these (Core i7-2600K) has only 8MB of L3 cache per processor (less than most of the 2010 Mac Pros). These will probably begin shipment in early 2011 (based on production schedule estimates [66] and a later Intel announcement [78]), which is somewhat more than 2 years after the debut of Nehalem with the first Core i7 products.

At IDF 2010, Intel presented a roadmap showing that the Sandy Bridge systems would be introduced into mainstream, budget and portable market segments well before the "enthusiast" (high end desktop) and workstation/server segments [78]. Therefore a Mac Pro based on Sandy Bridge will not come until (at earliest) late 2011 — and possibly significantly later.

The most relevant Sandy Bridge CPUs are code-named "Romley". AnandTech predicts[79] that Intel may release 4-core Sandy Bridge based Xeon processors in "the middle" of 2011, but that an 8-core Sandy Bridge part is unlikely to appear until the end of 2011 "at the absolute earliest". The new Xeon-EP would use the upcoming, larger LGA 2011 socket, which has 4-channel DDR3 memory (see [69] and [77]) to provide the needed higher memory bandwidth. Some sources (e.g. [75]) refer to a "Sandy Bridge EN" Xeon for the LGA 1366 socket, occupying a small niche in between high-end desktop and standard 2-socket server. If this is a real product (and not something specialized like a blade server CPU) then Apple might choose it.

Apple's Pro refresh schedule has been slowing down significantly over the past several years [89], and I consider it likely that they actually want to wait at least a year after the August 2010 models before offering a Sandy Bridge model.

In the meantime I suspect that Intel will move more of its Xeon line over to the 32-nm process, producing 4-core Xeon-EN CPUs that are price-competitive with the current 45-nm W3530 and W3565 used in the entry-level 4-core Mac Pros. Apple would probably switch over to these without changing the price or anything else in the system.

The 8-core "Beckton" designs, the 10-core 32nm Westmere Xeon-EX [74], and any Sandy Bridge replacements thereof, are all expected to be aimed at the 4-socket server market where the price per CPU is much higher, mainly because of their vastly higher transistor count and correspondingly lower yield.

However, Apple has also been rumored to be looking at AMD alternatives [68]. The current Mangy-Cours models (8-core and 12-core) and forthcoming designs like Bulldozer (including the 16-core Interlagos) seem like good possibilities. All are one thread per core, although the Bulldozer design blurs the distinction between cores and threads.

Apple's Special Relationship With Intel

On several occasions it has been clear that Apple has been able to get certain part numbers from Intel a little ahead of the rest of the industry. Recent examples include:

2007 Jan: The Pentium M "Crofton" used in Apple TV (see macnn [23]).
2007 Apr 4: The 3.0 GHz Xeon X5365 "Clovertown" used in the first 8-core Mac Pro (see electronista [24]).
2008 Apr 29: The 3.07 GHz Core 2 Extreme X9100 "Penryn", used in the top-model iMac months before being released to the general market on July 14. (see TG Daily [32]).
2008 Jan: The original MacBook Air's 1.6 and 1.8 GHz processors (described by Anand: [28] and [29]).
2009 Mar 3: The first Nehalem-based Mac Pros, using Xeon processors (the W3520, W3540, E5520, X5550 and X5570 or (by some accounts) X5580) about 3 weeks before being available to the general market (see TG Daily [53]).

Before Apple became a major customer of Intel, a similar type of relationship existed with IBM regarding the PowerPC G5 (the 970, 970FX, and 970MP).

In May 2011, a special Apple-Intel relationship was confirmed directly [87] by Intel's Tom Kilroy, who stated:

"We work very closely with them and we're constantly looking down the road at what we can be doing relative to future products. I'd go as far as to say Apple helps shape our roadmap"

Appendix A

Charts and Tables of Intel-CPU-Specific History

Tick Tock Chart

This chart illustrates the general pattern of alternation between the development of semiconductor processes (see the lithography table below) and changes in computer architecture, illustrated by the past 20 years of Intel CPU history.

The pattern of new semiconductor fabrication processes is the most regular; the chart attempts to show the very first product for each new process, with source references in most cases.

For each new process, one representative microarchitecture change (or sometimes two) is shown.

Generation	fab.	Server	Workstation	High-end	Desktop	Mobile	First representative product	Apple example
microarch.:	1 uM		-	-
new process	0.8 uM		-	-			1991 Jun 24 (80486 50 MHz, see [9])
microarch.:	0.8 uM		-	-
new process	0.6 uM		-	-			1994 Mar 7 (80486 DX4 75 MHz, see [7] and [9])
microarch.:	0.6 uM		-	-
new process	0.35 uM		-	-			1995 Mar 27 (Pentium 133 MHz, from [7])
microarch.:	350		-	-
new process	0.25 uM		-	-	Deschutes		1997 Sep 8 (mobile Pentium MMX 200,233 MHz, see [8])
microarch.:	250		-	-	Katmai
new process	0.180 uM		-	-	Coppermine	Coppermine	1999 Jun 14 (low volume production of the 400 MHz Mobile Pentium II, see [10]) 1999 Oct 25 (Pentium III, see [12])	iMac G4 (early 2002)
microarch.: Coppermine	180	Willamette	-	-	Willamette	Coppermine	2000 Nov 20 (Pentium 4 1.4 and 1.5 GHz using Socket 423)
new process	0.130 uM	Northwood	-	-	Northwood	Tualatin	2001 Jul 30 (mobile Pentium III 1.13 GHz, see [16]; sampled in May[15])	iBook G4 (fall 2003)
microarch.: hyperthreading	130 nm		-	-	Northwood	Banias	2002 Nov 14 (Pentium 4 3.06GHz)
new process	90nm		-	-	Prescott	Dothan	2004 Feb 1 (Pentium 4 2.80 GHz, Pentium 4 HT 2.8E and 3.0E, see [18])	PowerMac G5 (PCI-X 2)
microarch.:	90		Irwindale	Smithfield	Prescott 2M	Dothan	2005 Feb
new process (and Pentium-M)	65nm	Tulsa	Dempsey	Presler	Cedar Mill	Yonah	2006 Jan 5 (Core Solo T1300 and several Core Duos)
microarch.: Core 2	65	Tigerton	Clovertown	Kentsfield	Conroe	Merom	2006 Jul 27 (Core 2 Duo E6300-E6700)	MacBook Pro (October 2006)
new process	45nm	Dunnington	Harpertown	Yorkfield	Wolfdale	Penryn	2007 Nov 12 (Core 2 Extreme QX9650 and 12 Xeon 54xx models) and several Xeon models, see [26])
microarch.: Nehalem	45	Beckton	Gainestown	Bloomfield	Lynnfield	Clarksfield	2008 Nov 17 (Core i7-920, i7-940 and i7-965)	Mac Pro (early 2009)
new process	32nm	Westmere-EX	Westmere-EP	Gulftown	Clarkdale	Arrandale	2010 Jan 7
microarch.: Sandy Bridge	32	SNB-EX (LGA-2011)	SNB-EP (LGA-1356)	SNB-EP	SNB-DT (LGA-1155)	SNB-NB	2011 Jan 9 (Core i7-2630QM through 2820QM)	MacBook Pro (early 2011)
new process	22nm						expected early 2012 ("Ivy Bridge")
microarch.: Haswell	22						probably early 2013

The main driving force behind these alternating cycles is the learning curve of process technology, and in particular the improvements in yield related to declining defect rate.

Because of initial low yields, a new process will be used only for products that:

have smaller transistor counts (small die size)

can be configured during burn-in by disabling defective sections and still be sellable, and/or

can be sold for a high price

Any combination of these factors, together with market factors in the different product segments (embedded, mobile, desktop, server, etc.) can determine which market segment will get the new fab technology first. The third criterion (selling for a higher price) often drives this decision, and higher price is usually justified because of the benefits that smaller-scale fabrication provides:

same performance with lower power consumption (ideal for mobile and server markets), or

greater performance within any given power/heat limits by being able to run at a higher speed (an important driving force up until the "4 GHz wall" changed everything in 2004-2006) or by running at full speed a greater percentage of the time.

Whenever a given process reaches the point where yields are competitive with the previous (larger) process on a transistor count basis, it is possible to move existing products to the new process. This is a process shrink, and it happens at a point that is planned well in advance and timed to address market factors. As just mentioned, the process shrink allows for better power consumption and/or greater speed. As the yield learning curve continues to improve, the new process allows for cheaper manufacturing cost as well (because the product now fits on a physically smaller die).

As fabrication yields continue to improve, the new fab process enters the period during which it is cheaper on a transistor-count basis but still more expensive on a die-area basis. During this period, another unvarying principle takes place, namely the fact that more transistors can always provide a benefit. Thus, during this period the various products undergo one or more microarchitecture changes. Each microarchitecture change is planned well in advance and incorporates everything R&D has been able to figure out they can do with a given transistor budget. By the (eventual) time yields allow producing the same die size for the same cost, the transistor budget approaches 2× what it was in the established microarchitectures of the previous process technology.

By this time, another new, yet smaller process technology is ready to begin low-volume production and the entire cycle repeats.

New Process Announcements

Following are excerpts from press releases and independent reports on each of the past several generations of fabrication processes.

0.35 micron :
The Pentium Processor 120 MHz is the first volume microprocessor to be built using a 0.35 micron process technology [...]
   Intel's move to volume microprocessor manufacturing on a 0.35 micron process technology is an industry first. It allows the die size to be reduced to approximately one-half the size of Intel's Pentium processors built on 0.6 micron process technology (75, 90, and 100 MHz) which was introduced just last year, or about one-fourth the size of the original Pentium processors built on the 0.8 micron technology (60 and 66 MHz) introduced in 1993.
   Intel's 0.35 micron process technology is a 3.3 volt BiCMOS process that combines the energy-saving features of CMOS technology and the high-performance characteristics of bi-polar technology. The process features four layers of metal and full use of planarization (polishing each surface of the wafer flat before building the next layer upon it), and is built on 8-inch (200mm) wafers.
   — Intel press release[7], 1995 Mar 27

0.25 micron :
The new 200- and 233-MHz mobile Pentium processors with MMX technology are the first products manufactured using Intel's advanced 0.25 micron process technology. [...] The impressive increase in performance and decrease in power consumption of 200- and 233-MHz mobile Pentium processors with MMX technology are attributed primarily to the benefits of Intel's new 0.25 micron manufacturing technology. The 0.25 micron manufacturing process and Intel's Voltage Reduction Technology decrease the core voltage from 2.45 volts to 1.8 volts and the I/O interface from 3.3 volts to 2.5 volts relative to previous generation processors. This reduction in voltages is a key element in enabling the production of faster processors that consume less power.
— Intel press release[8], 1997 Sep 8

0.18 micron :
The mobile Pentium II processor at 400 MHz is Intel's first processor built using Intel's 0.18 micron manufacturing process. [...] The 0.18 micron manufacturing process allows the processor to become smaller, faster and more powerful than its 0.25 micron predecessors.
   Intel's 0.18 micron process technology features industry-leading transistor performance using transistor gate lengths as small as 0.14 microns, a 2 nanometer (20 angstrom) gate oxide thickness and a CoSi2 (cobalt silicide) layer for low resistance. Interconnects feature six layers of aluminum and a low capacitance SiOF insulator for high performance. [...]
   — Intel press release[10], 1999 Jun 14 [...] The good news is that the transition from 0.25-micron to 0.18-micron is going very smoothly. Part of the reason for this is because Intel started the transition to 0.18-micron very early on. On June 14, 1999, Intel released their first 0.18-micron CPU, the mobile Pentium II 400.
   — AnandTech[11], 1999 Oct 25
Intel is the first company in the industry to begin high-volume manufacturing utilizing 0.18-micron process technology. Intel is using this technology in four factories around the world. The 0.18-micron process technology features structures that are smaller than 1/500th the thickness of a human hair, smaller than bacteria and smaller than the visible wavelength of light (for the human eye). The smallest structures on this new process are as small as 0.13-microns. Intel's new 0.18-micron process technology uses six layers of aluminum metal interconnect, a low SiOF (fluorine-doped silicon dioxide) capacitance interconnect insulator, and can feature voltages as low as 1.1 to 1.65 volts (the lowest voltage of the products introduced today is 1.35 volts).
   — Intel press release[12], 1999 Oct 25

0.13 micron (130 nm) :
Intel Corporation today announced five new processors based on Intel's advanced 0.13-micron (130 nanometer) process technology [...] are available in volume today at speeds up to 1.13 GHz, the industry's fastest speed for mobile processors.
   By incorporating its advanced 130-nanometer process technology, Intel is able to build transistors (the switches used to create the ones and zeroes of the information age) that are the fastest in the industry. This new process technology also features high speed copper interconnects that accelerate the flow of data inside the processor, further increasing performance while consuming less power.
   Processors built on Intel's 130-nanometer technology consume up to 40 percent less power and are up to 20 percent faster than the previous 180 (0.18-micron) nanometer process. Chips using Intel's 130-nanometer technology contain circuitry that is about 1/1000th the width of a human hair (1000 nanometers equal 1-micron).
   — Intel press release[16], 2001 Jul 30

90 nm :
Intel's first 90nm processor is here and after delays and much waiting, we're getting much more than we bargained for. If you thought this chip was just a larger cache on a smaller process you were dead wrong...
   AnandTech[17], 2002 Feb 1
Intel's 90 nm (a nanometer is one-billionth of a meter) process technology is the most advanced semiconductor manufacturing process in the industry, built exclusively on 300 mm wafers. This new process combines high performance, low-power transistors, strained silicon, high-speed copper interconnects and a new low-k dielectric material. This is the first time all of these technologies have been integrated into a single manufacturing process.
   Intel® Pentium® 4 processors built on the 90-nm process retain the multitasking capabilities of Hyper-Threading (HT) Technology, and include new features such as enhanced Intel® NetBurst® microarchitecture, a larger, 1 MB Level 2 (L2) cache and 13 new instructions.
   — Intel press release[18], 2004 Feb 2

65 nm :
[The] all-new 65 nm Pentium Extreme Edition 955 based on Presler [uses] on a state-of-the-art manufacturing process, comes with double the L2 cache (2× 2 MB rather than 1× 1 MB), an accelerated system clock speed (FSB1066 instead of FSB800) and a core clock speed increase of approximately 8.25%. [It has] 376 million transistors [on] two Cedar Mill type single core [dies].
   [benchmark tests and results were here]
   Intel's business has been going well. However, its reputation suffered considerably when it failed to realize in time that the public would resist the literally hot 90 nm NetBurst portfolio. [...] Intel is in a good position [with] its progress in 65 nm manufacturing. Not only do the smaller structures allow for ramping up production volumes, but they also clearly help to decrease heat dissipation and power consumption. [...] The latest Extreme Edition processor underscores the premise that manufacturing technology is what matters most in the processor business. 65 nm enables Intel to make up for the flaws in its current 90 nm portfolio and to deliver competitive products over the coming months.
   — Tom's Hardware[20], 2005 Dec 28

45 nm :
Called the biggest transistor advancements in 40 years by Intel Co-Founder Gordon Moore, the processors are the first to use Intel's Hafnium-based high-k metal gate (Hi-k) formula for the hundreds of millions of transistors inside these processors. These Intel® Core^TM 2 Extreme and Xeon® processors are also the first to be manufactured on the company's 45-nanometer (nm) manufacturing process, further boosting performance and lowering power consumption.
Combining these two advancements with new processor features enables Intel to continue delivering faster and more energy-efficient processors that are better for the environment. The breakthroughs clear the path for Intel to design products that are 25 percent smaller than previous versions and, thus, more cost-effective, as well as the ability next year to pursue new ultra mobile and consumer electronics "system on chip" opportunities.
— Intel press release[26], 2007 Nov 11

32 nm :
The introduction of new Intel® Core^TM i7, i5 and i3 chips coincides with the arrival of Intel's groundbreaking new 32 nanometer (nm) manufacturing process — which for the first time in the company's history — will be used to immediately produce and deliver processors and features at a variety of price points, and integrate high-definition graphics inside the processor. This unprecedented ramp and innovation reflects Intel's $7 billion investment announced early last year in the midst of a major global economic recession.
   Intel is unveiling several platform products, including more than 25 processors, wireless adapters and chipsets, including new Intel Core i7, i5 and i3 processors, [all] manufactured on the company's 32nm process, which includes Intel's second-generation high-k metal gate transistors. This technique, along with other advances, helps increase a computer's speed while decreasing energy consumption.
   New Intel Core i7 and Core i5 processors also feature exclusive Intel Turbo Boost Technology for adaptive performance, [and] Intel® Hyper-Threading Technology, available in Intel Core i7, Core i5 and Core i3 processors [...]
   — Intel press release[64], 2010 Jan 7

The Pentium MMX microarchitecture adds:

Microarchitecture Innovations

Earlier microarchitectures added: pipeline, cache, floating-point unit, 2X or faster internal bus.

The P5 (original Pentium) microarchitecture implements the following improvements over the 80486:

More efficient microcode control of pipeline for block copy and some other instructions
Superscalar execution (ability to run two instructions through separate pipelines provided they don't interfere with each other)
Faster math (e.g. full hardware multiply for integer and floating-point)
More capable address calculation unit
Less latency handling virtual 8086 mode
Separate level 1 data and instruction caches
64-bit external data bus (twice that of the 80486)

Adds MMX instructions (an integer-only 64-bit vector unit)
Doubles the level 1 cache sizes

The P6 (Pentium Pro) microarchitecture:

Adds speculative execution and out-of-order completion
Increases pipeline stages from 5 to 14
Uses register renaming to make pipeline more efficient
Has dedicated cache (256K or 512K, later 1M) on separate die(s) inside the CPU package, for higher speed (as compared to the previous third-party cache solutions)
Uses dual independent buses (both 64 bit) to access cache and main memory simultaneously

The Pentium III microarchitecture:

Decreases pipeline from 14 stages to 10

The Coppermine (180 nm Pentium III) microarchitecture:

Adds 256K level 2 cache on the same die

The Netburst (P68) microarchitecture:

Increases pipeline stages to 20
Uses double-speed ALUs
Adds an execution trace cache to reduce need to decode micro-ops
(Starting with 3.06 GHz) Adds hyperthreading (two program counters and two copies of all user registers, with larger reorder buffer and reservation station to support dispatching two unrelated instruction streams at once)

The Pentium M microarchitecture came together with a process shrink, for the mobile segment's transition to 65nm. The Pentium M microarchitecture:

Increases the L2 cache size
Adds the SSE2 instructions
Has a 12-14 pipeline stages (less than Netborst but still more than Pentium III)
Branch predictor now has global history
Micro-ops fusion for more efficient handling of certain complex x86 instructions

The Core microarchitecture:

Adds the SSE3 instructions
Expands cache interface to allow 2 cores
Decreases pipeline to 12 stages (always)

Core 2 is the new microarchitecture for 65 nm process, and the first microarchitecture since P5 to be used across the entire product line. Core 2:

Adds 64-bit instructions and more user registers (x86-64 extensions)
Adds two pipeline stages (from 12-stage to 14-stage) to allow significantly higher clock rates
Adds capacity throughout the pipeline: more instruction decoding, reorder, issue and scheduler capacity
Increases FP units from 1 FMUL/FADD to 1 each FMUL, FADD, FLOAD and FSTORE
Increases SSE units from 1 to 3
Adds one integer ALU
Has a larger L2 cache (increased from 2M in Yonah Core Duo to 4M in Merom Core 2 Duo)

Process shrink Penryn also adds the first version of Turbo Boost, called "Intel Dynamic Acceleration", for mobile CPUs only.

The Nehalem microarchitecture:

Has more efficient macrofusion, loop stream detecting and branch prediction [47]
Brings back hyperthreading (larger reorder buffer and reservation station, twice as many user registers, etc)
Puts all cores on a single die (as compared to Core 2 Quad)
Adds Turbo Boost, which increases the clock speed of those cores that are being used whenever one or more cores is idle.
Switches to a three-level cache design (256K L2 cache private to each core and large shared L3 cache; formerly one large L2 cache shared by each pair of cores)
Replaces FSB with direct memory interface and QPI for massively greater bandwidth

Process shrink Westmere also adds processor graphics in the package (but not on the same die as the CPU).

The Sandy Bridge microarchitecture:

Adds a GPU on-die (primarily for mobile and low-end desktop segment)
Doubles load/store capacity
Doubles SIMD capacity (256-bit AVX instructions)
Adds a ring bus interconnect between cores, cache, GPU and memory controller (similar to Beckton)

Process shrink Ivy Bridge will also add PCIe 3.0, USB 3.0 and/or a larger GPU (depending on which product)

The Haswell microarchitecture:

Will probably have improved processor graphics (details unknown)
Will have an improved cache design (details unknown: could include longer cache lines, wider data paths, lower cycle latencies, and/or larger overall size)
Will add FMA (fused multiply add) instructions

Overview of Recent Intel Codenames

For the most part, each Intel microprocessor codename refers to a particular microarchitecture (design) on a particular process (lithography feature size). This table summarizes the codenames, by process (rows) and microarchitectures (columns):

	Pentium 4	Pent. 4 HT	(Pentium D)	Pentium M, Core	Core 2 Duo	(Quad)	Core i7	2^nd-Gen. Core	(future)	(future)
180 nm	Willamette Nov 2000
130 nm	Northwood Jan 2002	Northwood HT Nov 2002		Banias
90 nm		Prescott Feb 2004	(Smithfield)	Dothan May 2004
65 nm		Cedar Mill	(Presler)	Yonah Jan 2006	Conroe Aug 2006	(Kentsfield)
45 nm					Wolfdale Jan 2008	(Yorkfield)	Nehalem Nov 2008
32 nm							Westmere Jan 2010	Sandy Bridge Jan 2011
22 nm								Ivy Bridge 2Q 2012	Haswell

italics = "Tick", boldface = "Tock" in the Intel marketing department's "Tick-Tock" metaphor. Each "Tick" is below the preceding "Tock", and the subsequent "Tock" is to its right.

A "Tick" is the move to a smaller lithography, usually allowing for better power efficiency and sometimes added cache, or small feature enhancements that don't change the whole design (examples: a few new instuctions to speed encryption, or adding PCIe 3.0 to the integrated Northbridge functions).

According to Intel, their long-term goals in process technology development are to develop the next smaller size (fitting twice the transistors in the same area) every two years. When a new process is just starting to be productive, existing designs are the best designs to try to produce, because it is already well-known how those designs respond to irregularities in lithographic steps and because existing designs make for a smaller die size than any newer, upcoming designs.

A "Tock" is a new microarchitecture, allowing for better performance with (roughly) the same yield and transistor count, or for much better performance using a larger transistor count. Releasing a new microarchitecture only after the new lithography process has matured (i.e. during the year "in-between" Ticks) makes sense, and will naturally occur even if it is not planned that way, simply due to market forces and the allocation of limited development resources.

The "Tick-Tock" metaphor was first used by Intel marketing[22] in 2006, but the pattern can be easily seen to extend back before that time. Each "tick" has come near the beginning of an even-numbered year, and until Sandy Bridge each "tock" came near the end of the same year. (Thus the wait from a "tock" to the next "tick" is usually a bit longer).

Most of the codenames shown above are for the mainstream desktop variants, with the notable exception of Pentium M. Pentium M was the mobile version of Pentium III, marketed alongside the desktop processor Pentium 4. The difficulty in getting Pentium 4 to run on low power budget led to Pentium M continuing into the days of the Pentium 4 HT (with HyperThreading) and Pentium D (dual-core). The Pentium 4 and Pentium D microarchitecture design was abandoned when it became clear that the path towards the "terahertz transistor" was unsustainable due to heat dissipation, and the transition to "many" (4 or more) power-efficient cores in the desktop CPU was inevitable.

I have included two non-Tock columns that I consider significant: the Pentium D (first dual cores) and the Core 2 Quad (first quad cores). The Pentium D "Smithfield" was almost exactly two "Prescott" cores side by side on a die, linked to each other only through the shared front side bus that connects off-chip to the Northbridge. Similarly, a Core 2 Quad is little more than two Core 2 Duo dies in the same package, linked by the front side bus.

As of mid 2011, the 22nm lithography process seems to be on-track for production, but I anticipate that the "Haswell" developments might be delayed a bit if 22nm takes longer to reach yield maturity. In such a case, another codename (perhaps also ending in "bridge") might occupy a spot between Ivy Bridge and Haswell.

If 22nm successfully reaches high yields in large scale production, the next pocess technology will be 16nm, which Intel (as of their 2011 May 22 nanometer press event) is still calling "14nm".

Brief Chronology of Intel Silicon Fabrication Process Technology

year	process	nominal feature length	wafer size	speed	product	transistors
1971	"p234"	10 µM	50 mm	740 KHz	4004	2250
1974	"p338"	6 µM	75 mm	2.0 MHz	8080	6000
1976	"p442"	3 µM	100 mm	5.0 MHz	8085	6500
1978		3 µM	100 mm	5.0 MHz	8086	29,000
1982	"p546"	1.5 µM	125 mm	6.0 MHz	80286	134,000
1985	P646	1.5 µM	150 mm	16 MHz	80386	275,000
1989	P648	1.0 µM	150 mm	25 MHz	80486	1,180,000
1993	P650	0.8 µM	150 mm	66 MHz	Pentium P5	3.1 million
1994	P852	0.6 µM	200 mm	100 MHz	Pentium P54C	3.3 million
1994		0.5 µM	200 mm	100 MHz	Pentium P54C	3.3 million
1995	P854	0.35 µM	200 mm	120 MHz	Pentium Pro	5.5 million
1997	P856	0.25 µM	200 mm	233 MHz	Pentium II Deschutes	9.5 million?
1999	P858	0.18 µM	200 mm	500 MHz	Pentium III Coppermine	29 million
2001	P860 P1260	130 nm	200 mm 300 mm	1133 MHz	Pentium III Tualatin	29 million
2004	P1262	90 nm	300 mm	2.8 GHz	Pentium 4 Prescott	125 million
2006	P1264	65 nm	300 mm	2.17 GHz	Core Duo T2600	151 million
2008	P1266	45 nm	300 mm	2.67 GHz	Core 2 Duo E8200	410 million
2010	P1268	32 nm	300 mm	2.93 GHz	Core i3-530	382 million
2012	P1270 P1870(?)	22 nm	300 mm 450 mm	~ 3.1 GHz	(Ivy Bridge)	~ 880 million
2015?	P1272(?) P1872	16 nm	300 mm 450 mm

Sources: Wikipedia Transistor count, Pentium (and other similar articles, see the Wikipedia references below), and some of the sources listed under the lithography table

Actual Transistor Densities

This chart shows the variation between nominal transistor density (as expressed by a technology name like "0.13 micron" or "32 nanometer") and the actual density of transistors in CPU products over the entire history of the microprocessor.

Based on the size of a chip and the number of transistors (both are usually well-known, see list of sources after the table) the density in transistors per square centimeter is computed by the formula:

density = transistors / area

Then the effective process size is computed by the following formula:

effective size = K / √density

The constant K is adjusted so that the effective size, on average, corresponds to the official process size. Currently K is about 72000.

release process size	density	process size
19710000
19720000
19740000
19740000
19760000
19760000
19780000
19780000
19790000
19790000
19820000
19851017
19890410
19900507
19930122
19941010
19950300
19950601
19951101
19960300
19970108
19970300
19970507
19980824
19980800
19990226
19991025
20001100
20010400
20010600
20020100
20020708
20030600
20031103
20040300
20040510
20041108
20050220
20050501
20060100
20060600
20060718
20070107
20070121
20070422
20070608
20071111
20080106
20080325
20080529
20080915
20081113
20081117
20090108
20090325
20090601
20090602
20090908
20100107
20100208
-
-
-
-
20100208
20100316
20100329
20100330
20100427
20100316
20100920
20110109
20110220
20110220
20110300
20110403
20110509
20111012
20111114
20120600
20120600
-
-
-
-

date name nominal
transistors    die size    transistor
   effective
source; alias(es); other notes Intel 4004 10000 2300 13 mm² 176.92 6172. 108 KHz clock Intel 8008 10000 3500 15 mm² 233.33 5374. 250 KHz clock Intel 8080 6000 6000 20 mm² 300.00 4739. 2.0 MHz clock RCA 1802 5000 5000 27 mm² 185.19 6032. Intel 8085 3000 6500 20 mm² 325.00 4553. Zilog Z80 4000 8500 18 mm² 472.22 3777. Motorola 6809 5000 9000 21 mm² 428.57 3965. Intel 8086 3000 29000 29 mm² 1000.0 2596. 5 to 10 MHz Intel 8088 3000 29000 29 mm² 1000.0 2596. Motorola 68000 4000 68000 44 mm² 1545.5 2088. Intel 80286 1500 134000 69 mm² 1942.0 1862. 6 to 12 MHz Intel 80386DX-16 1500 275000 104 mm² 2644.2 1596. Intel 80386DX-33 1000 275000 39 mm² 7051.3 977.6 Intel 80486DX-33 1000 1180000 163 mm² 7239.3 964.8 Pentium 60MHz 800 3100000 294 mm² 10540 799.5 Original P5 Pentium 75 600 3300000 163 mm² 20250 576.9 P54C Pentium 120 350 3300000 163 mm² 20250 576.9 P54CQS: smaller transistors but same die dize: wasted space on die due to packaging constraints Pentium 133 350 3300000 90 mm² 36670 428.7 P54CS Pentium Pro 150 500 5500000 306 mm² 17970 612.3 AMD K5 500 4300000 271 mm² 15870 651.7 Pentium MMX 166 280 4500000 128 mm² 35160 437.8 Pentium Overdriv 150 280 4500000 140 mm² 32140 457.9 die size uncertain Pentium II 233 350 7500000 203 mm² 36950 427.1 "Klamath" Pentium II 266A 250 7500000 113 mm² 66370 318.6 "Deschutes" Celeron 300A 250 19000000 154 mm² 123400 233.7 SL2WM "Mendocino" (128K cache on-die) Pentium III 450 250 9500000 128 mm² 74220 301.3 "Katmai" (512K cache on separate chips) Pentium III 500E 180 28000000 106 mm² 264200 159.7 "Coppermine" (256K cache on-die) Pentium 4 1.3 180 42000000 217 mm² 193500 186.6 SL5FW "Willamette", socket 423 Pentium 4 1.7 180 42000000 217 mm² 193500 186.6 SL67A "Willamette", socket 478 Pentium III-S 1000 130 44000000 80 mm² 550000 110.6 "Tualatin" with 512K cache on-die Pentium 4 1.6A 130 55000000 131 mm² 419800 126.7 SL668 "Northwood A" Itanium 2 1000 180 221000000 421 mm² 524900 113.3 McKinley Itanium 2 1400 130 410000000 374 mm² 1096000 78.40 SL6XE "Madison" (6M cache) Pentium 4 EE 3.2 130 169000000 237 mm² 713100 97.22 "Gallatin" Pentium 4 505 90 125000000 112 mm² 1116000 77.71 SL7YU "Prescott", socket 478 Pentium M 735 90 144000000 87 mm² 1655000 63.81 SL7EP "Dothan" (2M cache) Itanium 2 1600 130 592000000 432 mm² 1370000 70.13 Madison 9M Pentium 4 630 90 169000000 135 mm² 1252000 73.37 SL8Q7 "Prescott 2M", LGA 775 Pentium D 840 XE 90 230000000 206 mm² 1117000 77.69 SL88R "Smithfield" Pentium D 631 65 188000000 81 mm² 2321000 53.88 SL9KG one "Cedar Mill" core (2M cache) Pentium D 965 XE 65 376000000 162 mm² 2321000 53.88 SL9AN "Presler" (two Cedar Mill cores) Itanium 2 9050 90 1720000000 596 mm² 2886000 48.32 SL9PG Montecito Core 2 Quad Q6600 65 582000000 286 mm² 2035000 57.55 SLACR "Kentsfield" (two Conroe dies each with 4M cache) Core 2 Duo E4300 65 167000000 111 mm² 1505000 66.93 SLA99 "Allendale" (2M cache) Core 2 Duo E6320 65 291000000 143 mm² 2035000 57.55 SLA4U "Conroe" (4M cache) IBM POWER6 65 789000000 341 mm² 2314000 53.97 8M of cache on-die Xeon X5450 45 820000000 214 mm² 3832000 41.93 SLBBE "Harpertown" Core 2 Duo E8400 45 410000000 107 mm² 3832000 41.93 SLB9J "Wolfdale" (6M cache) Core 2 Quad Q9550 45 820000000 214 mm² 3832000 41.93 SLB8V "Yorkfield" (two Wolfdale dies each with 6M cache) VIA Nano 65 94000000 63 mm² 1492000 67.20 "Isaiah" (1M cache) Xeon X7460 45 1900000000 503 mm² 3777000 42.24 SLG9P "Dunnington" AMD Opteron 2384 45 705000000 263 mm² 2681000 50.14 "Shanghai" Core i7-940 45 731000000 263 mm² 2779000 49.24 SLBCK "Nehalem/Bloomfield", the original Core i7 (LGA 1366) AMD Phenom II X4 45 758000000 258 mm² 2938000 47.89 Anand-4118 "Deneb" Xeon W5580 45 731000000 263 mm² 2779000 49.24 SLBF2 "Nehalem-EP" AMD Athlon II X2 45 234000000 117 mm² 2000000 58.05 "Regor" AMD Opteron 2400 45 904000000 346 mm² 2613000 50.79 "Istanbul" Core i5-750 45 774000000 296 mm² 2615000 50.76 SLBLC "Lynnfield" (LGA 1156 Nehalem) Core i5-650 32 382000000 81 mm² 4716000 37.80 SLBTJ "Clarkdale" Itanium 9350 65 2046000000 699 mm² 2927000 47.98 Tukwila core logic 65 430000000 276 mm² 1558000 65.77    core logic: 95 watts; 0.34 W/mm² cache 65 1420000000 191 mm² 7435000 30.10    L3 cache: 40 watts ; 0.21 W/mm² interconnect 65 152000000 107 mm² 1421000 68.88    system interconnect: 30 watts; 0.28 W/mm² I/O 65 39000000 123 mm² 317100 145.7    I/O (QPI, memory, SMI): 20 watts; 0.16 W/mm² IBM POWER7 45 1200000000 567 mm² 2116000 56.43 8 cores and 32M of eDRAM (not SRAM) cache Core i7-980X 32 1170000000 239 mm² 4895000 37.10 SLBUZ "Gulftown" AMD Opteron 6176 SE 45 1808000000 692 mm² 2613000 50.79 "Magny-cours" (two Thuban dies in one package) Xeon X7560 45 2300000000 684 mm² 3363000 44.77 "Beckton" or "Nehalem-EX" AMD Phenom II X6 45 904000000 346 mm² 2613000 50.79 Anand-4118 "Thuban" Xeon X5680 32 1170000000 248 mm² 4718000 37.79 "Westmere-EP" Sun SPARC T3 40 1000000000 377 mm² 2653000 50.40 Core i7-2600 32 995000000 216 mm² 4606000 38.25 Anand-4818 "Sandy Bridge", "2nd Gen. Core". 4 cores, 8M cache, 12-core GPU. (1.16B transistors as-fabbed) Core i3-2110 32 624000000 149 mm² 4188000 40.11 Anand-4118 2 cores, 4M cache, 12-core GPU ("HD graphics 3000") (727M transistors as-fabbed) Core i3-2100 32 504000000 131 mm² 3847000 41.85 Anand-4118 2 cores, 3M cache, 6-core GPU ("HD graphics 2000") (588M transistors as-fabbed) VIA Nano X2 65 188000000 136 mm² 1382000 69.82 Anand-4017 (trans. count is a guess) Xeon E7-8870 32 2600000000 513 mm² 5068000 36.46 "Xeon E7" or "Westmere-EX" VIA Nano X2 E-series 40 188000000 66 mm² 2848000 48.64 40nm die-shrink of older Nano X2 (trans. count is a guess) AMD FX-8150 32 1200000000 315 mm² 3810000 42.06 "Bulldozer" (8-core desktop), 16M cache Core i7-3960X 32 2270000000 435 mm² 5218000 35.93 Anand-5091 "Sandy bridge-E" (6-core desktop version), 15M cache VIA Nano X4 40 376000000 132 mm² 2848000 48.64 Anand-4332 Two 40nm X2 dies in one package (Future Itanium) 32 3153000000 544 mm² 5796000 34.10 "Poulson" (date estimated) core logic 32 712000000 158 mm² 4506000 38.67    core logic: 95 watts; 0.60 W/mm² cache 32 2173000000 163 mm² 13331000 22.48    L3 cache: 5 watts ; 0.03 W/mm² interconnect 32 224000000 137 mm² 1635000 64.20    system interconnect: 50 watts; 0.36 W/mm² I/O 32 44000000 68 mm² 647100 102.0    I/O (QPI, memory, SMI): 20 watts; 0.29 W/mm²

Notes:

1 : Intel originally announced that a 4-core Sandy Bridge processor had "995 million" transistors (see [83]) and later (see [88]) they started using a larger figure, "1.16 billion". The larger figure is more relevant, so the other Sandy Bridge figures (originally quoted as "624 million" and "504 million") have been increased by a factor of 1160/995.

Things to Note

The first chips on each new process tend to have a smaller die size. Larger die sizes come later, after the yield rate has improved.

Cache generally improves transistor density. For example, looking at the Core 2 Duos that were made on 65nm process, the one with more cache has a significantly higher transistor density.

I do not know why the Itaniums "Montecito" and "Tukwila" have the same transistor density, while one is called "90nm" and the other is called "65nm". I think Intel should call them both "65nm". The cache sizes are known to be the same and the die of the older Montecito has been seen without the heat spreader.

In the nominal and effective process size columns, the number is in boldface if it sets a new record (representing a significant (more than 5%) increase in density over anything up to that date).

The effective process size numbers stay fairly close to the "nominal" process size all the way back to the mid 1970's. However, in recent years (2003 through 2011) the effective process size has diminished only by about a factor of 2.7 (from 102 for the Pentium 4 "Gallatin" to 38 for the Xeon E7) rather than a factor of 4 as the process names (130 to 32) would suggest.

To help explain part of this, I have broken down two Itanium models (the 65-nanometer Tukwila from 2010 and the forthcoming 32-nanometer Poulson) into four parts (thanks to an article from Real World Technologies[86]). Shown are the transistor densities and power usage of the cache, CPU cores, internal communications and external I/O sections of the Tukwila and Poulson chips. For both Itaniums, the cache is by far the most dense section. Note also that the power density in watts per square millimeter (W/mm²) for the cache is far less for Poulson than for Tukwila — this is the result of the far lower idle leakage current of the high-k metal gate transistors.

The system interconnect (busses that connect the cores to the caches and the I/O) are very busy and have a very high power density despite their much lower transistor density. In Tukwila the interconnects are only a little less dense than the cores, but in Poulson they are far less dense, yet still have a rather high power density.

This difference in density between different parts of the CPU has always existed. However, in the 1970's through 1990's, heat was only a minor concern; but more recently power consumption and heat have become very important factors. It is because of this that the interconnect (most especially) cannot be shrunk as quickly as the cache.

Back in the early Pentium-4 period, the overall power density of CPU chips (in watts per square millimeter) began to reach the limit of how much heat could be taken off the chip by the cooling system (heat sink and fan). In the period since then, power usage for idle transistors has diminished significantly, but power usage by active transistors has not decreased as much; also the total bandwidth (data transfer capacity) and raw calculation power of the processors has continued to increase. For these reasons, the actual CPU cores have not gotten much smaller, and nearly all of the benefit of the smaller-scale process technologies has gone into the relatively cooler cache (where almost all of the transistors remain idle almost all of the time).

Sources

Intel's database of products, ark.intel.com

Many Wikipedia articles, including Transistor count and many articles on individual brands and codenames such as List of Intel Core i7 microprocessors, Sandy Bridge, Itanium, etc.

TechArp's comparison guides

The ChipList

CPU World helped fill the gap on Intel 386 and 486.

I get most of my brand-new data from AnandTech, for example this article was the first place I got the January 2011 Sandy Bridge figures, and this article explains the discrepancy between "995 million" and "1.16 billion". Their articles on recent multi-core VIA Nano chips are here: [80], [85].

Approximate Chronology of Memory Products and Process Technology

This table is from 20001100 Iwai.jpg, who cites the 1999 ITRS Roadmap. There are other similar tables in more recent ITRS Roadmaps.

year	feature length	bits	transistors
1971	10 µM	1 Kib	2200
1974	6 µM	4 Kib	8500
1977	4 µM	16 Kib
1980	3 µM	64 Kib
1983	2 µM	256 Kib
1986	1.2 µM	1 Mib
1989	0.8 µM	4 Mib
1992	0.5 µM	16 Mib
1996	0.35 µM	64 Mib
2000	0.25 µM	256 Mib
2003		1 Gib
2006	50 nm	4 Gib
incomplete

Recent Memory Module Characteristics and Performance

name	memory clock (MHz)	cycle time (ns)	I/O clock (MHz)	data rate (MT/s)	module name	bandwidth (GB/s)

3.3V SDR:
SDR-66	67	15	67	67	PC66	0.533
SDR-100	100	10	100	100	PC100	0.800
SDR-133	133	7.5	133	133	PC133	1.067

2.5V DDR:
DDR-200	100	10	100	200	PC-1600	1.600
DDR-266	133	7.5	133	267	PC-2100	2.133
DDR-333	167	6	167	333	PC-2700	2.667
DDR-400	200	5	200	400	PC-3200	3.200

1.8V DDR2:
DDR2-400T	100	10	200	400	PC2-3200	3.200
DDR2-533T	133	7.5	267	533	PC2-4200	4.267
DDR2-667T	167	6	333	667	PC2-5300	5.333
DDR2-800T	200	5	400	800	PC2-6400	6.400
DDR2-1066T	267	3.75	533	1067	PC2-8500	8.533

1.5V DDR3:
DDR3-800T	100	10	400	800	PC3-6400	6.400
DDR3-1066T	133	7.5	533	1066	PC3-8500	8.533
DDR3-1333T	167	6	667	1333	PC3-10600	10.67
DDR3-1600T	200	5	800	1600	PC3-12800	12.80
DDR3-1866T	233	4.29	933	1867	PC3-14900	14.93
DDR3-2133T	267	3.75	1067	2133	PC3-17000	17.07

T denotes latency timing: number of clock cycles to start a transaction. The letters are: B=3, C=4, D=5, E=6, F=7, G=8, H=9, J=10, K=11, L=12, M=13, N=14. For example, the timings on a "DDR3-1600H" module are 9-9-9.

Sources: Wikipedia: Dynamic random access memory, Synchronous dynamic random access memory, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM

Appendix B

Lithography Details

year (products shipping)	process	nominal feature length	gate length	light source	wave	energy	Technology introduced in this process
1971	"p232"	10 µM
1974	"p336"	6 µM
1974	"p338"	4 µM
1976	"p440"	3 µM
1982	"p542"	2 µM
1982	"p544"	1.5 µM
1989	P648	1.0 µM	1.0 µM	Hg	400 nm (violet)	3.1 eV
1991	P650	0.8 µM	0.8 µM	Hg	400 nm	3.1 eV
1993	P652	0.6 µM		Hg	400 nm	3.1 eV
1993	P852	0.5 µM	0.5 µM
1995	P854	0.35 µM	0.35 µM	Hg KrF	400 nm 248 nm	3.1 eV 5.0 eV
1997	P856	0.25 µM	0.20 µM	KrF	248 nm	5.0 eV
1999	P858	180 nm	0.13 µM	KrF	248 nm	5.0 eV	Low-k dielectric between interconnects
2001	Px60	130 nm	70 nm	KrF ArF	248 nm 193 nm	5.0 eV 6.4 eV	copper interconnects
2003	P1262	90 nm	50 nm	ArF	193 nm	6.4 eV	strained silicon
2005	P1264	65 nm	40 nm	ArF	193 nm	6.4 eV	alternating phase-shift masks
2007	P1266	45 nm	35 nm	ArF	193 nm	6.4 eV	double patterning, High-k dielectric (hafnium-based) with metal gate
2010	P1268	32 nm	30 nm	ArF	193 nm	6.4 eV	immersion
2012?	P1870	22 nm	25 nm	ArF	193 nm	6.4 eV	FinFETs (non-planar devices)
2015?	P1872	16 nm		ArF?			Intel calls this "14 nm".
2019?	P1874	11 nm		?			might not be reached, or perhaps will be implemented with doubly stacked 16nm devices

Process names and data are from Wikipedia pages (click the links "130 nm", "90 nm", etc.) and also references: [13], [14], [21]

Performance Myths

Megahertz / Gigahertz

This is pretty well known by now — a higher clock speed (in MHz or GHz) does not guarantee better performance. This is mainly a problem when comparing different types of processors, like AMD vs. Intel or (in the old days) Pentium vs. PowerPC. It is also a significant problem with certain brand names. For example, while it is reasonable to assert that, for example, a "2.5 GHz Core 2 Duo" is faster than a "1.8 GHz Core 2 Duo", a similar comparison between a "2.5 GHz Xeon" and a "1.8 GHz Xeon" is virtually meaningless, because the Xeon brand name has been in use for such a long time. (Compare the Core 2 and Xeon lists).

Core Count and/or Thread Count

Now that it has been accepted that clock speeds are pretty much stuck in a fixed range (for desktop systems, around 2 to 4 GHz), a new "core count myth" (and with Hyperthreading, a "thread count myth") has become fashionable.

To illustrate the core count and thread count myths, here is a comparison of two systems that have the same core and thread characteristics (2 cores, 4 threads) but are spaced 4 years apart:

June 2006	May 2010
Presler CPU dies The Pentium Extreme Edition 965 (SL9AN) is a Presler CPU, which has two Cedar Mill dies in a single package.	Westmere CPU die This is the CPU die of the Clarkdale Core i3-550 (SLBUD). (Clarkdale's graphics, on a separate die, does not factor into the SPECint benchmarks)
process: 65 nm transistors: 188 million per die, 376 million total die area: 162 mm² (2×81) density: 2.32 million per mm² thermal budget: 130W	process: 32 nm transistors: 382 million die area: 81 mm² density: 4.72 million per mm² thermal budget: 73W
Report name: cpu2006-20060513-00012.txt System: Dell, Inc. Precision 380 Workstation CPU Name: Intel Pentium Extreme Edition 965 CPU(s) enabled: 2 cores, 1 chip, 2 cores/chip, 2 threads/core CPU MHz: 3733 L1: 12 K micro-ops I + 16 KB D on chip per core L2: 2 MB I+D on chip per core L3: None Memory: 4 GB (4x1 GB 667MHz ECC CL5 DDR2 SDRAM) Disk: 1 x 80GB SATA 7200 RPM SPECint_rate_base2006: 23.1	Report name: cpu2006-20100820-13042.txt System: Fujitsu PRIMERGY TX150 S7, Intel Core i3-550, 3.20 GHz CPU Name: Intel Core i3-550 CPU(s) enabled: 2 cores, 1 chip, 2 cores/chip, 2 threads/core CPU MHz: 3200 L1: 32 KB I + 32 KB D on chip per core L2: 256 KB I+D on chip per core L3: 4 MB I+D on chip per chip Memory: 8 GB (2x4 GB PC3-10600E, 2 rank, CL9-9-9, ECC) Disk: 1 x SAS, 300 GB, 10000 RPM SPECint_rate_base2006: 61.2

The newer system is a 3.2 GHz Core i3-550, and it scores about 2.5 times higher on this benchmark. This is despite the fact that the older system has a higher clock rate (3.733 GHz). The Core i3-550 does not have Turbo Boost, so it is really running at 3.2 GHz.

The Dell Precision 380 was an entry-level server ($949). The Fujitsu PRIMERGY TX150 S7 costs a bit more, but not for reasons that matter here. (For example it comes with 8 bays for hot-swap hard drives, but none was installed for the test).

The 3.2 GHz Core i3 is able to trounce the older 3.7 GHz system because it has:

Many architectural improvements (shorter pipeline, more execution units, more efficient hyperthreading, etc.),
Larger L1 cache,
Lower-latency L2/L3 cache (but of the same size, 4M total),
Faster memory (2×10.67 GB/sec vs. 5.33 GB/sec) and driven directly by the processor,
Faster disk (SAS 10000 RPM vs. SATA 7200 RPM)

All of these, not just core and thread counts, affect overall performance — and most of these differences are determined by the CPU chip itself. Therefore — since both systems have the same numbers of cores and threads — we must conclude that "performance = core count" and "performance = thread count" are myths.

Similarly, this example also disproves the old "performance = clock speed" myth, and other similar myths like "performance = transistor count" and "performance = cache size".

MacBook Pro, Early or Mid 2011 (speculation)

Appendix C: Old Speculations

Those wishing to see how far off-base I was can compare the following to what actually came to pass.

(written in 2010 October)

In early 2011, Intel is expected to offer processors based on the Sandy Bridge microarchitecture to follow the current Arrandale models, sharing the "Core i5" and "Core i7" brand. These add several improvements, notably:

An integrated GPU with much better performance than that of the present-generation (Arrandale) GPU,

256-bit vector capability to perform twice as many floating-point operations per clock cycle (as compared to SSSE3),

A high-speed inter-core ring bus design inherited from Beckton (Xeon 75xx series, see [76]).

All will provide substantial performance boosts for MacBook Pro users, and each targets different applications. The ring bus is perhaps the most general, because it allows each of the 5 main components (CPU cores, L3 cache, GPU, memory, and PCI devices) to communicate at full speed with each of the other 4, all at the same time.

Such changes push power usage, but Sandy Bridge also includes power management improvements, with substantial gains just from putting the CPU and GPU on a single 32nm die. The imagined future MacBook Pro models shown here use the 35W parts listed on the Wikipedia Sandy Bridge page. All are 2-core processors with hyperthreading. (More cores should become possible on a 35W power budget only after a future process shrink to 22nm.) Note that the first Sandy Bridge announcements will be 4-core (see [82]) mainly for marketing reasons.

I believe Apple will get rid of the discrete NVIDIA GPU (the GT 330M) in at least some of the new models because the Sandy Bridge "2-core" (12 shader units) graphics is known to be comparable to a desktop Radeon HD 5450 (see references: [71],[73]), or a mobile NVIDIA GeForce GTX 460M (see [81]), which should come close to or exceed the GT 330M due to the far superior memory interface and cache bandwidth offered by putting the CPU and GPU on the same die (see GPU comparisons on Wikipedia: NVIDIA, AMD/ATI).

The Core 2 Duo processor should also go away, inasmuch as both chips currently being used (the P8600 and P8800) as well as all versions used in earlier MacBook Pros will have been discontinued[70] or "End-of-Life"d by then. That means the 13'' will get a Core i3 or i5. (This probably does not apply to the MacBook Air, because it uses a special smaller-packaged Core 2 Duo likely to be retained for the embedded market.)

See my 2011 Mac Pro speculation for more about Sandy Bridge, including more links to sources.

MacBook Pro Sandy Bridge (speculation)

(These CPUs will probably replace only the high end of the MacBook Pro line, with Arrandale Core i3 or i5 being used for the rest)

CPU: Core i5 2520M (2.5-3.2 GHz), 2540M (2.6-3.3 GHz) or Core i7 2620M (2.7-3.4 GHz)

Cores/Threads: All new models have 2 cores and 4 threads

L3-Cache: 3MB (Core i5 versions) or 4MB (Core i7)

Bus and Memory: 1.333 GHz DDR3 SDRAM

Mac Pro, Late 2011 (speculation)

(written in 2010 July)

Intel is expected to offer processors based on the Sandy Bridge microarchitecture to follow the Gainestown, Westmere and similar generation Nehalem processors. These will continue to use the 32-nm process but will add improvements to the core, notably a 256-bit vector unit capable of performing twice as many floating-point operations per clock cycle. This and other core changes will place higher demands on the cache and memory system, so it is unlikely the number of cores will change because the transistor budget will need to shift somewhat in favor of memory interface, cache, and I/O. On some Sandy Bridge products this transistor budget will include integrated GPU functions [67], but Mac Pro is likely to use the server-type products without the GPU.

The first Sandy Bridge processors will probably begin shipment in early 2011 (based on production schedule estimates [66]), which is somewhat more than 2 years after the debut of Nehalem with the first Core i7 products. Therefore a Mac Pro based on Sandy Bridge would come a bit more than 2 years after the first Nehalem Mac Pros, and possibly significantly later. Apple's Pro refresh schedule has been slowing down significantly over the past several years [89], and I consider it likely that they will wait at least a year after the August 2010 models before offering a Sandy Bridge model.

The 8-core "Beckton" designs and any Sandy Bridge replacements thereof, and the 12-core "Eagleton" version of Xeon-EX [57] are both expected to be aimed at the 4-socket server market where the price per CPU is much higher, mainly because of their vastly higher transistor count and correspondingly lower yield..

However, Apple has also been rumored to be looking at AMD alternatives, and the 6-core "bulldozer" design and others like it seem like a possibility.

Mac Pro, Summer 2010 (speculation)

(written in 2009 October and 2010 February)

The single-processor desktop Nehalem product will move up to a 6-core "Gulftown" implementation in conjunction with its transition to the 32-nm process "later in 1Q 2010"[65]. This product was rumored to be branded "Core i9" [60]) but is now believed to be a future "Core i7-980X" [61] or perhaps keeping the "Core i7 Extreme" branding) [58]. Xeon EP is also scheduled to transition to 32-nm, but that won't happen until significantly later. On the Intel roadmap briefing from 2009 Feb 10^th it looks like the end of 2010, or perhaps even a bit later.

However, prior to that time the 8-core "Beckton" Xeon EX will have been released on the 45-nm process. It is easy to speculate that Apple could decide to offer one or more high-end Mac Pro or Xserve products based on it. However, such speculation is highly unrealistic. The Beckton design has twice as many cores, but more than three times as many transistors (2.3×10⁹ vs. 7.3×10⁸ for the 4-core "Gainestown"[56]) and this drives production cost way up because of yield considerations. Beckton also requires special "memory buffers" that are not needed in Gainestown designs[55], and there are other things that make the overall system design costlier. Because it is designed for a 4-socket system (4 Beckton chips on the motherboard), putting two of them into a 2-socket system like the Mac Pro would be a waste, and Intel prices it with this in mind: there is no way Apple could offer any product anywhere near the prices of its current products using two Beckton CPUs.

It is also possible that Intel will release a Xeon EP 45-nm product with more cores, however sources[59],[60] indicate this is highly unlikely and that the 32-nm Westmere process is being used instead. (A 6-core 45nm part would use too much power to be practical, unless its clock speeds were significantly lower).

Rumors in October 2009[60] indicated that Apple might yet again have a special deal with Intel allowing them to get the 6-core Nehalem EP sooner. The same sources also indicate that larger memory modules will be officially supported, allowing systems with 64GiB or 128GiB.

However Apple's slow schedule for updating the Mac Pro, combined with the comparatively low pressure to add a "mere" 1.4x performance boost that the Gulftown would provide, makes me think this update won't come until summer, maybe at the WWDC.

Beyond 2010 : Looking further, there is a 12-core "Eagleton" version of Nehalem-EX expected a year or two after the 8-core Xeon EX [57].

MacBook Pro, Early 2010 (speculation)

(written in 2010 January)

An Intel leak[62] makes it seem very likely that Nehalem-based mobile CPUs under the Core i5 brand will be used in a future MacBook Pro. Unlike desktop Core i5s, which lack the hyperthreading feature, Mobile Core i5 CPUs have 2 cores and 4 threads [63].

MacBook Pro Core i5 (speculation)

CPU: Core i5 540M "Arrandale" (3.06 GHz) ($257)

L3-Cache: 3M

Bus: 1.066 GT/sec

Memory: 1.066 GHz PC2-8500 DDR2 SDRAM

Mac Pro, Early 2009 (speculation)

(written in 2009 February)

The "Harpertown" versions in the Jan 2008 Mac Pros came out in November 2007. Along with several other projects (such as the Penryn chips used in the 2008 MacBooks) it uses the new 45-nm process with Hafnium hi-k MOSFET gates. (The 32-nm process, currently still in development during 2009, uses similar chemistry and should be able to easily reach 4.0 GHz, a "holy grail" hitherto achieved only with liquid cooling rigs).

As of November 2008, it now seems likely that Intel and Apple are moving on to Core i7 (code named Nehalem), rather than new steppings of the Harpertown and similar Core 2-based Xeon designs. The reader should note that "Nehalem" (without a suffix) and "Core i7 desktop and notebook" products work only on single-socket motherboards. These are the CPUs initially released in November 2008; they lack the ability to communicate between two CPUs to keep their caches up to date.

Any computer built around a 2-socket or 4-socket motherboard is commonly called a "server". To the non-Apple part of the industry, the 8-core Mac Pro is a server system — as is any of the dual-socket Power Macs. Intel's current offerings for server motherboards are branded "Xeon DP" (dual processor) and "Xeon MP" (multi-processor). Mac Pro uses the Xeon DP 54xx series. The Nehalem "EP" processor, still promised for "1Q 2009", will work on two-socket motherboards, and will be sold under the "Xeon" brand name and with numbers in the 55xx range (W5580, X5570, E5540, etc.). It has the ability to snoop the cache of a second processor via the dedicated QPI/CSI link (discussed further below). The planned 8-core Nehalem "EX" processor, which will also be called "Xeon", is for 4-socket motherboards, and can handle complex multi-processor cache coherency situations. It replaces the current (pre-i7) solution for 4-socket boards which is the 6-core "Dunnington" (Xeon 74xx series) The Xeon EX chips will probably have numbers in the 75xx range. (Incidentally, there are also Intel "Xeon" processors without multi-CPU capability, designed for single-socket server systems. The only thing setting them apart from the desktop Core i7 processors is their support for ECC memory. They will have "35xx" numbers, like W3570 and W3520.)

Core i7 has architecture improvements that substantially improve power efficiency, and this allows a faster clock speed at the same power level (i.e. temperature). They also support 2-way simultaneous multithreading similar to that introduced in the 3.06 GHz Pentium 4. Two concurrent threads can share one core thanks to two complete sets of user and rename (writeback) registers. This makes the processor appear to have twice as many cores as seen by the operating system and application software. However, this requires improvements to the cache and memory system.

Core i7 indeed has a substantially faster PCMS⁵, making the 2-chip design much more practical by eliminating the Northbridge bottleneck. Each CPU chip now contains its own memory controller, with the memory DIMMs connecting directly to the processor. In a two-CPU server like the next Mac Pro, each CPU has half of the system memory. When accessing the other half of memory, access is slower. For this reason the OS is likely to use address translation to place each task's program and data within one CPU's memory when possible, and schedule its threads preferentially on that CPU's cores. A similar thing is already being done to optimize cache utilization (as can be seen by using Activity Monitor to watch the CPU usage on a dual-core system while running a single, non-multithreaded computation task.)

The memory controllers in these Nehalem CPUs use DDR3 (at 1033 or 1333 MHz) to communicate to RAM, and QuickPath Interconnect, also called CSI (Common System Interface) to communicate with the second processor and everything else outside the PCMS⁵. The DDR3 memory controller and the CSI, normally part of the Northbridge chip, is integrated into the CPU. (which is why the CPUs have such a large pin count). This makes the higher bus speed and wider (3x 64 bits) path to memory possible, and this in turn enables 4 cores to run with less cache on-chip. The total amount of cache is 1M of L2 and 8M of L3 shared among the 4 cores, which is less than the 12M that a Harpertown Core 2 Quad has, but with the faster memory this should be little problem.

The higher performance of the CSI-based method of sharing memory between two CPU chips is clear from benchmarks: a dual-socket, 8-core system based on the 3.4 GHz "Harpertown" X5492 has a CPU2006 fpbaserate of less than 90; a dual-socket 2.8 GHz Nehalem system scores 160⁶.

PCI-X (including any video cards) is handled by a new "bridge" chip of which Tylersburg is the first example. This page shows a few different examples of what's possible and also illustrates the DDR3 interface.

In addition to the major PCMS improvements, Apple can add plenty of other improvements to the system (e.g. the new Firewire IEEE 1394-2008, and perhaps even the long-awaited Blu-Ray Disc).

The move to Core i7 may come in the form of a "new flagship" update, similar to the introduction of the first 8-core Mac Pro in 2007 April, and the Power Mac G5 Quad in 2004 October. In both events the bottom and middle systems were quite similar in performance to their predecessors, and Apple added a new system at the top using a much better PCMS⁵.

Option 1, a single new flagship model based on Nehalem Xeon EP

CPU: 2x Xeon X5570 (2.93 GHz) or W5580 (3.2 GHz) $($1386 or $1600)$ (8 physical cores, 16 threads)

Cache: 2M L2 and 16M L3 (each 4 cores share 8M)

Bus: 6.4 GT/sec QuickPath

Memory: 1333 MHz DDR3 ECC

See AppleInsider

Additional Options (If moving more of the line to Nehalem)

CPU: 1x or 2x Xeon E5540 (2.53 GHz), X5550 (2.66 GHz) and/or X5560 (2.8 GHz) ($744 - $1172) (4 or 8 cores, 8 or 16 threads)

Cache: 256K of L2 per core and 2M of L3 per core

Bus: 6.4 GT/sec QuickPath

Memory: 1066 MHz DDR3 ECC (bottom model) or 1333 MHz DDR3 ECC (other models)

(Price details for the Xeon EP products: None of these prices had been announced yet when I made this prediction. I used two sources, wiki and rumor1. The details are: E5540 for $744 (wiki); X5550 for $958 (wiki) or $285 (rumor1); X5560 for $1172 (wiki); X5570 for $555 (rumor1) or $1386 (wiki); W5580 for $990 (rumor1) or $1600 (wiki). I find the lower prices suspicious because they are very similar to the existing "Core i7" prices. The Core i7 products do not work on two-socket motherboards.

Once these chips are actually shipping, they can be found by searching online shopping websites for their Intel product numbers. The Intel product number is "BX80602" plus the processor name, e.g. "BX80602E5540" for the E5540, or "BX80602W5580" for the W5580. )

MacBook Pro, Early 2009 (speculation)

(written in 2008 October)

In Oct 2008 Apple updated the 15-inch MacBook Pro (and also its consumer models, MacBook and MacBook Air) to use the newer Intel 45-nm "Penryn" processors with a 1.066 GT/sec bus to memory. When they did this they left the 17-inch MacBook Pro behind in regards to bus speed (and even processor speed — the 15-inch model offers a 2.8 GHz option, 17-inch is still either 2.5 or 2.6).

I suspect they will move this model up to the 2.8 GHz T9600, the 2.8 GHz processor used in the 15-inch MacBook Pro.

I also suspect they will make this update more attractive to top-end customers by offering a quad-core BTO option. I consider the gap in clock speeds between Q9100 and QX9300 to be suspiciously large, so I'm guessing Apple has a special deal on a 2.4 GHz "Q9200". In any event they need a chip that has a suitable package. FCBGA6 has not been used for anything over 35 watts TDP, but special Intel chips for Apple are not a new thing (the most relevant example is the original MacBook Air's 1.6 and 1.8 GHz processors (described in detail here); other examples include the 3.0 GHz Xeon X5365 "Clovertown" used in the first 8-core Mac pro (see this article); the 3.07 GHz Penryn released in 2008 April for the top-model iMac; and the Pentium M "Crofton" used in Apple TV (see here)). Such a processor would be 300 to 400 more expensive causing the price of the MacBook Pro to be, say $600 higher, but Apple has customers who would pay for it.

MacBook Pro 17-inch, 2009 (speculation)

CPU: Core 2 Duo "Penryn" T9600 (2.8 GHz) (2008 Jul 14: $530) or Core 2 Quad "Penryn QC" Q9200 (2.4 GHz) (2008 Late: exclusive)

L2-Cache: 6M or 12M (6M shared by each pair of cores)

Bus: 1.066 GT/sec

Memory: 1.066 GHz PC2-8500 DDR2 SDRAM

Early 2009 iMac (speculation)

(written late 2008)

Mobile versions of the Core 2 with 4 cores (Core 2 Quad) have been out since Aug 2008. Given Apple's intense work on the Snow Leopard (Mac OS X version 10.6) with its showcased OpenCL capability, it is likely that Apple will want to bring the consumer line up to 4 cores soon. I expect to see these chips move into both the iMac and the MacBook Pro, or their equivalents, very soon.

Rumors in November 2008 indicated that an additional line of lower-power desktop Core 2 Quads will also soon come out: the Q8200, Q9400 and Q9550. This is more likely to be the chip on which Apple will base its new iMacs.

iMac, early 2009 (speculation)

CPU: Core 2 Quad "Yorkfield" Q9400 (2.66 GHz) or Q9550 (2.83 GHz) (2009 Jan: $320 or $369)

L2-Cache: 6M or 12M (3M or 6M shared by each pair of cores)

Bus: 1.066 GT/sec

Memory: PC2-6400 (800MHz) DDR2 SDRAM

Larrabee iMac (speculation)

There is also Intel's planned Larrabee GPU, a graphics processor chip rumored for summer 2009 release that will compete well against ATI and NVidia, but also be more suitable for non-image computing tasks. It thus fits very well with OpenCL making performance under Snow Leopard (Mac OS X 10.6) even more impressive. This is most likely to see use in the iMac. There might also be a Mac Pro BTO option or an Intel video card.

I also think Apple is developing a new, fully 3-D window UI. An unannounced surprise (like the Quartz UI was before the official release of MacOS X), it will more closely resemble a CAD walkthrough than anything we've seen so far. Windows Aero's "Filp 3D" gives a taste.

Concerning MacBook Pro (speculation)

(written a week before the 2008 Oct 14 announcements)

Apple recently moved up from the 65-nm "Merom" family of Core 2 Duo processors to the 45-nm "Penryn" family, but are still on an 800 MT/sec bus to memory. I suspect they will move up the P8600, T9400 and/or T9600 that use a 1.066 GT/sec bus, but are otherwise similar to the present T8300, T9300 and T9500 chips. It's also about time they improved the speed of the memory frontside bus — PC2-6400 SODIMM prices are only marginally higher than PC2-5300.

In conjunction with the widely-rumored new case design (about which I care little, and you can read elsewhere) they may also be planning a quad-core option (perhaps using the Q9100 or QX9300) for a new flagship 17-inch MacBook Pro. I consider the gap in clock speeds between Q9100 and QX9300 to be suspiciously large, so I'm guessing Apple has a special deal on a 2.4 GHz "Q9200".

All of these chips (T8300 through QX9300) are of equal or very slightly faster clock speeds than the current line-up, and were added to Intel's product line in summer of 2008. The dual-core processors have the same price as the present ones. The quad-cores are much more expensive but Apple has customers who would pay for it. I'd guess they'll boost the memory speed even further for that model, too. Power usage is a big issue when you consider faster memory, which is probably why Apple has moved away from Intel's Montevina chipset (from AppleInsider [37]).

The case redesign probably is accompanied by manufacturing cost improvements enabling Apple to lower the prices slightly on the main line (by $100 or $200), making a little more room for the much higher price of the quad-core option.

MacBook Pro, 2008 Oct 14 (speculation)
option 1: low-end

CPU: Core 2 Duo "Penryn" P8600 (2.4 GHz) (2008 Jun 13: $241)

L2-Cache: 3M (shared by both cores)

Bus: 1.066 GT/sec

Memory: 800 MHz PC2-6400 DDR2 SDRAM

option 2: most likely 15-inch and 17-inch models

CPU: Core 2 Duo "Penryn" T9400 (2.533 GHz) or T9600 (2.8 GHz) (both 2008 Jul 14: $316, $530)

L2-Cache: 6M (shared by both cores)

Bus: 1.066 GT/sec

Memory: 800 MHz PC2-6400 DDR2 SDRAM

option 3: a new flagship quad-core 17-inch BTO option

CPU: Core 2 Quad "Penryn QC" Q9200 (2.4 GHz) (2008 Oct: exclusive)

L2-Cache: 12M (6M shared by each pair of cores)

Bus: 1.066 GT/sec

Memory: 1.066 GHz PC2-8500 DDR2 SDRAM

Concerning Mac Pro in Early 2009 (speculation)

(written in 2008 October)

The Harpertown versions in the Jan 2008 Mac Pros came out in November 2007 [26]. Along with several other projects (such as the Penryn chips used in the 2008 MacBooks) it uses the new 45-nm process with Hafnium hi-k MOSFET gates. This process should be able to reach 4.0 GHz (a "holy grail" hitherto unachieved with previous fabrication processes).

The Harpertown CPUs released in Sep 2008 (X5470 3.33 GHz and X5492 3.4 GHz) are too expensive for all but the top-model Mac Pro, but there is likely to be a new stepping with slightly higher voltage and the same power requirement, and consequentally higher yield, that will enable the existing speeds to be sold at a lower price. This happened across the entire Clovertown line when stepping G0 came out in July 2007 (see the Clovertown section of Wikipedia's Xeon list). Although no such imminent steppings are announced, Apple is known to have worked with Intel to get the first shot at a new production run through their close relationship with Intel (the most relevant example is the 3.0 GHz Xeon X5365 "Clovertown" used in the first 8-core Mac pro (reported by electronista [24]); other examples include the 3.07 GHz Penryn released in 2008 April for the top-model iMac; the original MacBook Air's 1.6 and 1.8 GHz processors (described by Anand: [28] and [29]); and the Pentium M "Crofton" used in Apple TV (on macnn [23])). There is also the leaked news (see here) that Intel will "update in early Q4'08" related to the current "Client platforms"; this most likely refers to a refresh of the existing Core 2 line, and high-end desktop Xeons are very likely to be included in that.

A modest improvement is possible, and likely sometime in the life-cycle of the 45-nm shrink/derivative families, by increasing the cache size. Intel has often come out with different lines of CPU chips that use essentially the same design and die layout but with differing clock speed, cache and bus interface.

So for early 2009 I predict Apple will offer clock speeds of 3.4, 3.2, and 3.0 or something similar, perhaps dropping the 3.0 clock speed to consolidate the line and make room for a new flagship (see below). PCMS⁵ specs will be otherwise unchanged, but Apple can add plenty of other improvements to the system (e.g. the new Firewire IEEE 1394-2008, and the long-awaited Blu-Ray Disc) to keep their customer base.

Mac Pro 8-core, early 2009 (speculation)

CPU: 2x Core 2 Quad "Harpertown" (3.0, 3.2 or 3.4 GHz)

L2-Cache: 24M (each pair of cores shares 6M)

Bus: 1.6 GT/sec

Memory: 800MHz DDR2 ECC fully buffered DIMM (FB-DIMM) RAM

New Flagship (speculation)

A mid-cycle "new flagship" update has happened twice in recent memory: the introduction of the Mac Pro 8-core in 2007 April, and the Power Mac G5 Quad in 2004 October. In both events the bottom and middle systems were unchanged or retained the same performance as their predecessors, and Apple added a new system at the top using a much higher-performance PCMS⁵. I call such a system a "new flagship" because of the attention it draws to the most demanding customers.

In late 2008, Intel will release some of the first Nehalem processors including certain Bloomfield and Gainestown products, under the Core i7 product name. Both are 4-core chips, using a new single-die layout, and they provide two significant improvements over everything mentioned above, simultaneous multithreading and a new memory system.

Intel refers to its implementations of simultaneous multithreading as "Hyper-Threading Technology", and the feature was last seen in the Pentium 4. Two concurrent threads can share one core thanks to two complete sets of user and rename (writeback) registers. This makes the processor appear to have twice as many cores as seen by the operating system and application software. However, this requires improvements to the cache and memory system. The Gainestown supports two CPUs (in two sockets linked by the motherboard — an 8-core system); Bloomfield is single-socket only. Intel is aiming the former at servers and the latter at high-performance desktops.

The memory system for all Nehalem CPUs uses DDR3 (at 1033 or 1333 MHz) to communicate to RAM, and QuickPath Interconnect, also called CSI (Common System Interface) to communicate with a second processor and everything else outside the PCMS⁵. The DDR3 memory controller and the CSI, normally part of the Northbridge chip, is integrated into the CPU. (which is why the CPUs have such a large pin count). This makes the higher bus speed and wider (3x 64 bits) path to memory possible, and this in turn enables 4 cores to run with less cache on-chip. The total amount of cache is 1M of L2 and 8M of L3 shared among the 4 cores, which is less than the 12M that a Harpertown Core 2 Quad has, but with the faster memory this should be little problem.

PCI-X (including any video cards) is handled by a new "bridge" chip of which Tylersburg is the first example. xtreview.com [25] shows a few different examples of what's possible and also illustrates the DDR3 interface. The initial Nehalems achieve 4.8 GT/sec through their CSI interfaces, later ones will be faster.

Another advance whose timing is about right to be part of this new flagship is use of the Intel Larrabee GPU, a graphics processor chip rumored for summer 2009 release that will compete well against ATI and NVidia, but also be more suitable for non-image computing tasks. It thus fits with the OpenCL part of Snow Leopard (Mac OS X 10.6). I also think they're developing a new, fully 3-D window UI. An unannounced surprise (like the Quartz UI was before the official release of MacOS X), it will more closely resemble a CAD walkthrough than anything we've seen so far. Windows Aero's "Filp 3D" gives a taste.

As for timing, it seems unlikely Apple would wait much more than a year after Intel's release of the new processors before using them — but it will be too soon after the early 2009 update to replace the whole line. So I suspect there will just be a single "New Flagship" Mac Pro.

Option 1, a new 8-core top model based on Gainestown

CPU: 2x Core i7 965 3.2 GHz ($999) (8 physical cores, 16 virtual cores)

Cache: 2M L2 and 16M L3 (each 4 cores share 8M)

Bus: 4.8 GT/sec QuickPath

Memory: 1066 MHz DDR3 ECC or 1333 MHz DDR3 ECC

See Fudzilla [46].

Option 1a, based on Bloomfield (will be used for 4-core models, if Apple decides to switch their entire line over to Nehalem)

CPU: single Core i7 940 "Bloomfield" 2.93 GHz ($562) (4 physical cores, 8 virtual cores)

L2-Cache: 1M L2 and 8M L3 (shared by the 4 cores)

Bus: 4.8 GT/sec QuickPath

Memory: 1066 MHz DDR3 ECC or 1333 MHz DDR3 ECC

See nV News [35], gizmodo [36], Tom's Hardware [44].

Additional Options (If moving more of the line to Core i7)

CPU: 1x or 2x Core i7 E5530 (2.4 GHz), X5550 (2.8 GHz) and/or W5580 (3.2 GHz) ($530 - $1600) (8 physical cores, 16 virtual cores)

Cache: 1M or 2M L2; 8M or 16M L3 (each 4 cores share 8M)

Bus: 4.8 GT/sec QuickPath

Memory: 1066 MHz DDR3 ECC (bottom model) or 1333 MHz DDR3 ECC (middle and top models)

see Tom's Hardware [44].

1 : AiO: "All-in-One": A desktop computer that contains the motherboard and a display, and sometimes other items too. The original Macintosh was an AiO, but on this page I am referring to it as a "Compact".

Footnotes

2 : Announced date shown only if different from Available date.

3 : PDA: "Personal Digital Assistant": I use this acronym, which dates from the Newton and Palm Pilot days, to describe the iPhone because of its similar form factor and functionality. Both are a good match to the all-in-one universal gadget predicted as far back as the late 1970's.

4 : These are the systems that I have owned (or used heavily at school or at work): Apple ][+, Mac 128, Mac 512KE, Mac IIsi, Powerbook 140, Centris 660AV, Power Mac 6100, Power Mac G3 (Blue and White), iMac G4 15", iBook G4 12", Power Mac G5 (dual 970fx), MacBook Pro 17" (Core 2 Duo), Mac Pro (8-core Nehalem), MacBook Pro 17" (4-core Sandy Bridge). With the exception of the Blue and White G3, I still own all of these systems, and all are in good working order except the iBook G4 (the dog knocked it off a table, it now crashes intermittently and cannot complete boot sequence).

5 : PCMS: Processor, Cache and Memory System. Other parts of the computer (graphics, hard disk, and I/O) are beyond the scope of this article and generally not a limiting factor for the types of workloads Apple addresses when they pick a faster processor.

6 : SPEC CPU2006 fp_base_rate from TechRadar [51].